#===- ./Makefile -------------------------------------------*- Makefile -*--===#

LEVEL=../..

main_target=$(BINDIR)/rbcp

include $(LEVEL)/Makefile.rules

MY_OBJ=$(LEVEL)/lib/.build/bc.bc $(BUILDDIR)/rbcp.bc

$(BINDIR)/rbcp: $(MY_OBJ) Makefile
	$(Echo) Linking $@
	$(Verb) mkdir -p $(BINDIR) && clang++ $(LDFLAGS) -o $@ $(MY_OBJ) $(LIBS)
